Conventional techniques for fabricating flash memory have been described in the U.S. Pat. Nos. 6,133,098 and 6,635,533.
As shown in FIG. 1, a typical flash memory has a select gate device 11 and a floating gate device 20 that share an impurity region. The floating gate device 20 is formed by sequentially depositing a tunneling oxide 2, a floating gate 3, a first gate dielectric layer 4, and a control gate 5 on a semiconductor substrate 1 at a predetermined width, and thereafter forming first spacers 6 on both sidewalls of the stacked structure including the control gate 5, the first gate dielectric layer 4, the floating gate 3, and the tunneling oxide layer 2.
A source/drain 7 is formed by implanting impurity ions within an area of the semiconductor substrate adjacent the stacked structure (i.e., the control gate 5, the gate dielectric layer 4, the floating gate, and the tunneling oxide layer 2).
The select gate device 11 is formed near one side of the above described floating gate device 20, so as to share the source/drain 7 with the floating gate device 20. The select gate device 11 includes a second gate dielectric layer 8 and a select gate 9 formed on the semiconductor substrate 1 at a predetermined width. It also includes second spacers 10 formed on both sidewalls of the second gate layer 8 and the select gate 9.
In the above described conventional flash memory cell, the floating gate 3 and the control gate 5 are sequentially deposited on the semiconductor substrate 1. As a result, the floating gate device 20 is a vertically extending structure 20 having a height (from the upper surface of the semiconductor substrate 1 to the upper surface of the control gate 5) which is higher than the height of the select gate device 11 (from the upper surface of the semiconductor substrate 1 to the upper surface of the select gate 9).
Accordingly, if an interlayer dielectric layer is formed on the entire surface of the semiconductor substrate including on the floating gate device 20 and on the select gate device 11, the interlayer dielectric layer will have an irregular surface topology. This irregular surface of the interlayer dielectric layer makes it difficult to form a contact at a precise position in a subsequent contact process.
Also, the conventional flash memory cell manufacturing method described above is disadvantageous in that the fabricated flash memory cell occupies a large area since the single floating gate is horizontally connected to the single select gate device.